In the manufacture of semiconductor products such as integrated circuits, individual electrical devices are formed on or in a semiconductor substrate, and are thereafter interconnected to form circuits. Interconnection of these devices within an integrated circuit is typically accomplished by forming a multi-level interconnect network in layers formed over the electrical devices, by which the device active elements are connected to other devices to create the desired circuits. Individual wiring layers within the multi-level network are formed by depositing an insulating or dielectric material layer such as SiO2 over the discrete devices or over a previous interconnect layer, and patterning and etching contact openings such as vias. A second pattern and etch defines trenches, the wiring between vias. Conductive material, such as copper is then deposited into the vias and trenches and planarized to form the next level of interconnect. Dielectric or insulating material then deposited over the patterned conductive layer, and the process may be repeated any number of times using additional wiring levels laid out over additional dielectric layers with conductive vias therebetween to form the multi-level interconnect network.
Integrated circuits used in radio frequency (RF) applications may contain inductors and capacitors in addition to the common use of transistors, diodes and resistors. Such integrated inductors and capacitors may be formed in the multi-level networks of the interconnect layers.
As device densities and operational speeds continue to increase and device scaling proceeds into the deep sub-micron regime, reduction of inductor and capacitor sizes in integrated circuits is also highly desired as these devices may require significant area within an integrated circuit to achieve the desired inductance (L) or capacitance (C). In addition, the location and structure of such passive devices may be particularly sensitive to stray capacitive coupling and noise, particularly when used as components of high input impedance or high gain circuits, high speed switching circuits, or RF integrated circuits.
Some prior art integrated inductor or capacitor designs use an associated solid conductive plate or shield layer. Such solid conductive layers may tend to develop eddy currents within the plates that needlessly consume power and degrade the efficiency of the device.
Accordingly, it is desirable to fabricate an improved inductor integrated within a semiconductor device.